ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 114

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

16-bit timer
114/324
3.
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t
f
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (See
CPU
EXT
Select the following in the CR2 register:
–
–
–
Reading the SR register while the ICFi bit is set.
An access (read or write) to the ICiLR register.
=
=
=
=
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see
Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see
= Pulse period (in seconds)
CPU clock frequency (in hertz)
Pulse period (in seconds)
External timer clock frequency (in hertz)
Doc ID 12370 Rev 8
event occurs
on ICAP1
OCiR Value =
Counter
= OC1R
When
When
OCiR =
One Pulse mode cycle
t
*
Figure
Table
f
EXT
OCMP1 = OLVL2
PRESC
OCMP1 = OLVL1
t
Counter is reset
ICR1 = Counter
*
ICF1 bit is set
f
CPU
-5
to FFFCh
50).
57).
- 5
ST72561-Auto
Table
50)