ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 118

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
16-bit timer
Note:
12.6
12.7
12.7.1
118/324
The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts
chapter). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
Summary of timer modes
Table 49.
1. See note 4 in
2. See note 5 in
3. See note 4 in
Register description
Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Read/ write
Reset value: 0000 0000 (00h)
Bit 7 = ICIE Input Capture Interrupt Enable.
Bit 6 = OCIE Output Compare Interrupt Enable.
Input capture
(1 and/or 2)
Output compare
(1 and/or 2)
One pulse mode
PWM Mode
ICIE
7
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
Modes
OCIE
Timer modes
One pulse mode
One pulse mode
Pulse width modulation mode
Input capture 1
TOIE
Yes
No
Doc ID 12370 Rev 8
FOLV2
Not
recommended
Not
recommended
Input capture 2
Yes
FOLV1
Timer resources
(1)
(3)
Output compare 1 Output compare 2
OLVL2
Yes
No
IEDG1
Partially
ST72561-Auto
Yes
No
(2)
OLVL1
0

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