ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 97

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Note:
Each input capture can generate an interrupt independently on a selected input signal
transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).
These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits
of the ARTICCSR register.
The read only input capture registers (ARTICRx) are used to latch the auto-reload counter
value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
After a capture detection, data transfer in the ARTICRx register is inhibited until the next
read (clearing the CFx bit).
The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means, the ARTICRx register has to be read at each capture event to
clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/f
During HALT mode, input capture is inhibited (the ARTICRx is never reloaded) and only the
external interrupt capability can be used.
The ARTICx signal is synchronized on CPU clock. It takes two rising edges until ARTICRx is
latched with the counter value. Depending on the prescaler value and the time when the
ICAP event occurs, the value loaded in the ARTICRx register may be different.
If the counter is clocked with the CPU clock, the value latched in ARTICRx is always the next
counter value after the event on ARTICx occurred
If the counter clock is prescaled, it depends on the position of the ARTICx event within the
counter cycle
Figure 44. Input capture timing diagram, f
ICAP SAMPLED
ARTICx PIN
COUNTER
CFx FLAG
f
COUNTER
f
(Figure
CPU
01h
45).
02h
Doc ID 12370 Rev 8
xxh
ICAP SAMPLED
03h
04h
COUNTER
(Figure
05h
= f
44).
CPU
PWM auto-reload timer (ART)
06h
COUNTER
05h
INTERRUPT
07h
).
t
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