ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 322

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Revision history
25
Table 129. Document revision history
322/324
03-May-2004
11-May-2004
12-May-2005
24-Oct-2005
Date
Revision history
Revision
1
2
3
4
Added TQFP 10x10 package
Removed internal RC
Updated
Added note on monotonous V
Added caution ART Ext clock not available in HALT see
reload timer (ART)
Added note “Once the OCIE bit is set both output compare features may trigger...”
and “Once the ICIE bit is set both input capture features may trigger...” in 8-bit timer
Section 13: 8-bit timer
Changed clock from fcpu/8000 to fosc2/8000 in
Changed description of CSR register to read only except bit 2 R/W
timer (TIM8)
Added note to SPI slave freq. and updated Master mode procedure in
Serial peripheral interface (SPI)
Changed description of NF bit in
Removed “Configurable timer resolution” under "Time triggered communication
option" from
Added Clearing interrupts limitation and SCI wrong break duration to
Important notes
Removed beCAN Time triggered mode feature from
(beCAN)
Renamed CMSR RX and TX bits to REC and TRAN in
(beCAN)
Added beCAN FIFO corruption limitation
Modified I
Modified Clearing interrupts limitation in
LIN
Changed name of WWDGR register to WDGWR in
Changed Static power consumption to 200 uA typ in
characteristics
Modified Readout Protection description in
Added
Modified
RESET pin protection when LVD is disabled
Added 48K ROM version in
Figure 154: ST72561xxx-Auto ROM commercial product structure
Added standard version 16K ROM/Flash devices
Modified data retention in
Added “6” and “3” standard version device type coding to
Auto Flash commercial product structure
commercial product structure
Modified power consumption
Added CDM in
Added “External interrupt missed”
SCI
TM
Section 24.1: All devices
changed to LINSCI
Figure 11: Clock, reset and supply block diagram
Figure 135: RESET pin protection when LVD is enabled
INJ
Section 17: beCAN controller (beCAN)
for Port B3 in
Electrostatic discharge (ESD)
Doc ID 12370 Rev 8
(TIM8).
Section 20.7: Memory characteristics
Section 20.9.1: General characteristics
Table 2: Product
TM
Section 20.4: Supply current characteristics
DD
throughout document.
Section 15.10: LIN mode register description
ramp on
Section 24.1.3: External interrupt missed
Changes
Chapter 24: Important notes
FIFO corruption
and
Section 5.6.1: Low voltage detector (LVD)
Section 3.3.1: Read-out protection
and related notes
overview,
Figure 154: ST72561xxx-Auto ROM
Section 13: 8-bit timer (TIM8)
Table 4: Hardware register map
Section 17: beCAN controller
Section 20.9.1: General
Section 17: beCAN controller
Figure 5: Memory map
Section 11: PWM auto-
Figure 152: ST72F561xxx-
and
Section 13: 8-bit
ST72561-Auto
Chapter 24:
Figure 136:
Section 14:
and