ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 69

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR
register has been set and the OIE bit in the MCCSR register is cleared (see
Main clock controller with real time clock MCC/RTC
Figure 29. AWUFH mode block diagram
As soon as HALT mode is entered, and if the AWUEN bit has been set in the AWUCSR
register, the AWU RC oscillator provides a clock signal (f
a fixed divider and a programmable prescaler controlled by the AWUPR register. The output
of this prescaler provides the delay time. When the delay has elapsed the AWUF flag is set
by hardware and an interrupt wakes up the MCU from Halt mode. At the same time the main
oscillator is immediately turned on and a 256 or 4096 cycle delay is used to stabilize it. After
this start-up delay, the CPU resumes operation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by software reading the AWUCSR register.
To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated
by measuring the clock frequency f
Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run
mode. This connects f
be measured using the main oscillator clock as a reference time base.
Similarities with halt mode
The following AWUFH mode behavior is the same as normal Halt mode:
●
●
●
●
The MCU can exit AWUFH mode by means of any interrupt with exit from Halt
capability or a reset (see
When entering AWUFH mode, the I[1:0] bits in the CC register are forced to 10b to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In AWUFH mode, the main oscillator is turned off causing all internal processing to be
stopped, including the operation of the on-chip peripherals. None of the peripherals are
clocked except those which get their clock supply from another clock generator (such
as an external or auxiliary oscillator like the AWU oscillator).
The compatibility of Watchdog operation with AWUFH mode is configured by the
WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog
RESET.
AWU_RC
f
AWU_RC
AWU RC
oscillator
divider
Section 7.4: Halt
to the ICAP1 input of the 16-bit timer, allowing the f
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AWU_RC
to Timer input capture
prescaler
and then calculating the right prescaler value.
AWUFH
/1 .. 255
mode).
for more details).
(ei0 source)
AWU_RC
AWUFH
interrupt
). Its frequency is divided by
Power saving modes
Section 10:
AWU_RC
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to