ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 43

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
5.5
5.5.1
output distortion and start-up stabilization time. The loading capacitance values must be
adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
Table 8.
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
●
●
●
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of three phases as shown in
●
●
●
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
External RESET source pulse
Internal LVD reset (Low Voltage Detection)
Internal watchdog reset
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
RESET vector fetch
ST7 clock sources
Doc ID 12370 Rev 8
C
Hardware configuration
L1
EXTERNAL
SOURCE
OSC1
OSC1
CAPACITORS
LOAD
ST7
ST7
Supply, reset and clock management
OSC2
OSC2
C
L2
Figure
12:
Figure
13:
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