ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 65

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
7.4
Figure 24. WAIT mode flow-chart
Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the
CC register are set to the current software priority level of the interrupt routine and
recovered when the CC register is popped.
Halt mode
The HALT mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see
MCC/RTC
AWUCSR register is cleared.
The MCU can exit HALT mode on reception of either a specific interrupt (see
RESET. When exiting HALT mode by means of a RESET or an interrupt, the oscillator is
immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or
by fetching the reset vector which woke it up (see
When entering HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In HALT mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction when executed while the Watchdog
for more details on the MCCSR register) and when the AWUEN bit in the
WFI INSTRUCTION
N
Doc ID 12370 Rev 8
INTERRUPT
Section 10: Main clock controller with real time clock
Y
OR SERVICE INTERRUPT
FETCH RESET VECTOR
256 OR 4096 CPU CLOCK
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
Figure
RESET
Y
26).
XX
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
10
10
1)
Power saving modes
Table
16) or a
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