ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 41

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ST72561J9-Auto

Manufacturer Part Number
ST72561J9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561J9-Auto

Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
ST72561-Auto
5
5.1
5.2
5.3
Caution:
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example, in case of a power brown-out), and reducing the number of external
components. An overview is shown in
For more details, refer to dedicated parametric section.
Main features
Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f
The PLL is not recommended for applications where timing accuracy is required.
Section 20.5.2: PLL characteristics
Figure 10. PLL block diagram
Optional PLL for multiplying the frequency by 2
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
System Integrity Management (SI)
4 Crystal/Ceramic resonator oscillators
Main supply Low voltage detection (LVD)
Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main
supply
f
OSC
Doc ID 12370 Rev 8
OSC2
Figure
PLL x 2
= f
/ 2
OSC
OSC2
11.
/2.
of 4 to 8 MHz. The PLL is enabled by option
PLL OPTION BIT
Supply, reset and clock management
0
1
f
OSC2
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