ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 232

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

beCAN controller (beCAN)
17.5
17.6
232/324
Interrupts
Two interrupt vectors are dedicated to beCAN. Each interrupt source can be independently
enabled or disabled by means of the CAN Interrupt Enable Register (CIER) and CAN Error
Interrupt Enable register (CEIER).
Figure 108. Event flags and interrupt generation
●
●
Register access protection
Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the following registers can be modified by
software only while the hardware is in initialization mode:
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and CDGR registers.
The FIFO interrupt can be generated by the following events:
–
–
–
The transmit, error and status change interrupt can be generated by the following
events:
–
–
–
–
Reception of a new message, FMP bits in the CRFR0 register incremented.
FIFO0 full condition, FULL bit in the CRFR0 register set.
FIFO0 overrun condition, FOVR bit in the CRFR0 register set.
Transmit mailbox 0 becomes empty, RQCP0 bit in the CTSR register set.
Transmit mailbox 1 becomes empty, RQCP1 bit in the CTSR register set.
Error condition, for more details on error conditions please refer to the CAN Error
Status register (CESR).
Wake-up condition, SOF monitored on the CAN Rx signal.
TXMB 0
TXMB 1
LECIEF
EWGF
RQCP
RQCP
WKUI
FOVR
BOFF
EPVF
FULL
FMP
EWGIE
EPVIE
BOFIE
LECIE
Doc ID 12370 Rev 8
+
&
&
&
&
+
WKUIE
TMEIE
FMPIE
FOVIE
ERRIE
CIER
FFIE
&
&
&
&
&
&
+
+
INTERRUPT
TRANSMIT/
ERROR/
STATUS CHANGE
INTERRUPT
ST72561-Auto
FIFO