ST72561J9-Auto STMicroelectronics, ST72561J9-Auto Datasheet - Page 48

• Manufacturer Part Number: ST72561J9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Supply, reset and clock management
5.6.5
48/324
Register description
System integrity (SI) control/status register (SICSR)
Read/Write
Reset value: 000x 000x (00h)
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag changes (toggles). The pending interrupt information is automatically cleared
when software enters the AVD interrupt routine.
Bit 5 = AVDF Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request
is generated when the AVDF bit changes value. Refer to
VDD main supply
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by hardware
(LVD reset) and cleared by software (writing zero). See WDGRF flag description for more
details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.
Bits 3:1 = Reserved, must be kept cleared.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to
ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the
LVDRF flag information, the flag description is given by the following table.
0: AVD interrupt disabled
1: AVD interrupt enabled
0: V
1: V
7
0
DD
DD
over V
under V
AVDIE
for additional details.
IT+(AVD)
IT-(AVD)
AVDF
threshold
threshold
Doc ID 12370 Rev 8
LVDRF
0
Figure 16
0
and to
0
Monitoring the
ST72561-Auto
WDGRF
0