W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 118

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

TC [18]: Terminal Count
0 = Channel does not expire
1 = Channel expires; this bit is set only by GDMA hardware, and clear by software to write logic 0.
TC [18] is the GDMA interrupt flag. TC [18] or GDMATERR[20] will generate interrupt
BLOCK [17]: Bus Lock
0 = Unlocks the bus during the period of transfer
1 = locks the bus during the period of transfer
SOFTREQ [16]: Software Triggered GDMA Request
Software can request the GDMA transfer service by setting this bit to 1. This bit is automatically
cleared by hardware when the transfer is completed. This bit is available only while GDMAMS [3:2]
register bits are set on software mode (memory to memory).
DM [15]: Demand Mode
0 = Normal external GDMA mode
1 = When this bit is set to 1, the external GDMA operation is speeded up. When external GDMA
TWS [13:12]: Transfer Width Select
00 = One byte (8 bits) is transferred for every GDMA operation
01 = One half-word (16 bits) is transferred for every GDMA operation
10 = One word (32 bits) is transferred for every GDMA operation
11 = Reserved
The GDMA_SCRB and GDMA_DSTB should be alignment under the TWS selection
SBMS [11]: Single/Block Mode Select
0 = Selects single mode. It requires an external GDMA request for every incurring GDMA operation.
1 = Selects block mode. It requires a single external GDMA request during the atomic GDMA
6.7.2.1. BME [9]: Burst Mode Enable
0 = Disables the 4-data burst mode
1 = Enables the 4-data burst mode
Ff there are 16 words to be transferred, and BME [9]=1, the GDMA_TCNT should be 0x04;
device is operating in the demand mode, the GDMA transfers data as long as the external GDMA
request signal nXDREQ1/2/3 is active. The amount of data transferred depends on how long the
nXDREQ1/2/3 is active. When the nXDREQ1/2/3 is active and GDMA gets the bus in Demand
mode, DMA holds the system bus until the nXDREQ1/2/3 signal becomes non-active. Therefore,
the period of the active nXDREQ1/2/3 signal should be carefully tuned such that the entire
operation does not exceed an acceptable interval (for example, in a DRAM refresh operation).
operation. An atomic GDMA operation is defined as the sequence of GDMA operations until the
transfer count register reaches zero.
- 115 -
W90N740CD/W90N740CDG
Publication Release Date: September. 19, 2005
Revision A7