W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 129

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

Host Controller Interrupt Enable Register (HcInterruptEnable)
Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit
unchanged.
Register: HcInterruptEnable
HcInterruptEnable
BITS
29-7
30
31
0
1
2
3
4
5
6
REGISTER
RESET
0b
0b
0b
0b
0b
0b
0b
0b
0b
0h
0xFFF0.5010
ADDRESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
SchedulingOverrunEnable
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
WritebackDoneHeadEnable
0: Ignore
1: Enable interrupt generation due to Write-back Done Head.
StartOfFrameEnable
0: Ignore
1: Enable interrupt generation due to Start of Frame.
ResumeDetectedEnable
0: Ignore
1: Enable interrupt generation due to Resume Detected.
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit are ignored.
FrameNumberOverflowEnable
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
RootHubStatusChangeEnable
0: Ignore
1: Enable interrupt generation due to Root Hub Status Change.
Reserved. Read/Write 0's
OwnershipChangeEnable
0: Ignore
1: Enable interrupt generation due to Ownership Change.
MasterInterruptEnable
This bit is a global interrupt enable. A write of ‘1’ allows interrupts to be
enabled via the specific enable bits listed above.
R/W Host Controller Interrupt Enable Register
R/W
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W90N740CD/W90N740CDG
DESCRIPTION
DESCRIPTION
0x0000.0000
VALUE
RESET