W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 59

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

When I-Cache is disabled, the cache memory is served as 8KB On-chip RAM.
The I-Cache is always disabled on reset.
The Features of the Instruction Cache：
Instruction Cache Operation
On an instruction fetch, bits 11～4 of the instruction’s address point into the cache to retrieve the tags
and data of one set. The tags from both ways are then compared against bits 30～12 of the instruction’s
address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match or
the matched tag is not valid, it is a cache miss.
6.4.3.1. Instruction Cache Hit
In case of a cache hit, bits 3～2 of the instruction address is used to select one word from the cache line
whose tag matches. The instruction is immediately transferred to the instruction unit of the core.
6.4.3.2. Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4-
word burst transfer read request. A cache line is then selected to receive the data that will be coming
from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the
selected set is invalid, then the least recently used line is selected for replacement. Locked lines are
never replaced. The transfer begins with the word requested by the instruction unit (critical word first),
followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound).
6.4.3.3. Instruction Cache Flushing
The W90N740 does not support external memory snooping. Therefore, if self-modifying code is written,
the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one
operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with
the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is
automatically flushed during reset.
6.4.3.4. Instruction Cache Load and Lock
The W90N740 supports a cache-locking feature that can be used to lock critical sections of code into I-
Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line
command.
To load and lock instruction, the following sequence should be followed:
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•
•
•
•
•
8K bytes instruction cache
Two-way set associative
Four words in a cache line
LRU replacement policy
Lockable on a per-line basis
Critical word first, burst access
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W90N740CD/W90N740CDG