W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 97

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

ALIE [5]: Alignment Error
Default value: 0
This bit is set if the frame length in bits was not a multiple of eight.
RXGD [4]: Receive Good
Default value: 0
This bit is set if a packet was successfully received with no errors.
PTLE [3]: Packet Too Long Error
Default value: 0
This bit is set if the MAC received a frame longer than 1518 bytes (unless ALP in MCMDR is set).
RXOV [2]: Receive FIFO Overflow error
Default value: 0
This bit is set if the MAC receives FIFO was overflow when receiving a frame.
CRCE [1]: CRC Error
Default value: 0
This bit is set if the CRC at the end of a packet is not correct, or else the PHY asserted Rx_er during
packet reception.
RXINTR [0]: Interrupt on Receive
Default value: 0
This bit is set if the reception of a packet caused an interrupt to be generated. This includes a good
received interrupt, if the EnRXGD bit in MIEN is set.
MAC General Status Register (MGSTA_0, MGSTA_1)
MGSTA_0
MGSTA_1
REGISTER
31
23
15
7
0xFFF0.30B8
0xFFF0.38B8
ADDRESS
30
22
14
6
Reserved
CCNT
29
21
13
5
R/W
R/W
R/W
28
20
12
4
MAC General Status Register
MAC General Status Register
Reserved
Reserved
- 94 -
W90N740CD/W90N740CDG
TXHA
DESCRIPTION
27
19
11
3
Reserved
SQE
26
18
10
2
RXHA
PAU
25
17
9
1
RESET VALUE
0x0000.0000
0x0000.0000
CFR
DEF
24
16
8
0