W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 128

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

Host Controller Interrupt Status Register (HcInterruptStatus)
All bits are set by hardware and cleared by software.
Register: HcInterruptStatus
HcInterruptStatus
BITS
REGISTER
29-7
30
31
0
1
2
3
4
5
6
RESET
0b
0b
0b
0b
0b
0b
0b
0h
0b
0h
0xFFF0.500C
ADDRESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
-
R/W Host Controller Interrupt Status Register
R/W
SchedulingOverrun
Set when the List Processor determines a Schedule Overrun has
occurred.
WritebackDoneHead
Set after the Host Controller has written HcDoneHead to
HccaDoneHead.
StartOfFrame
Set when the Frame Management block signals a ‘Start of Frame’
event.
ResumeDetected
Set when Host Controller detects resume signaling on a downstream
port.
UnrecoverableError
This event is not implemented and is hard-coded to ‘0.’ Writes are
ignored.
FrameNumberOverflow
Set when bit 15 of FrameNumber changes value.
RootHubStatusChange
This bit is set when the content of HcRhStatus or the content of any
HcRhPortStatus register has changed.
Reserved. Read/Write 0's
OwnershipChange
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
Reserved. Read/Write 0's
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W90N740CD/W90N740CDG
DESCRIPTION
Publication Release Date: September. 19, 2005
DESCRIPTION
RESET VALUE
0x0000.0000
Revision A7