W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 81

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

W90N740CD/W90N740CDG
EnTxBErr [24]: Enable Transmit Bus ERROR interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if system bus access error from Tx to system
memory occurred. If the interrupt is triggered, the Tx state machine will stay at Halt state. The software
reset is recommended while this interrupt occurred.
EnTDU [23]: Enable Transmit Descriptor Unavailable interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if transmit descriptors owned to the TxDMA is
unavailable. That means, if the TxDMA finds the ownership of descriptors is not belonged to TxDMA, it
will generate an interrupt and Tx operation will be ceased till the user issues a write command to
Transmit Start Demand register to restart Tx operation.
EnLC [22]: Enable Late Collision interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if a collision occurs after 512 bit times.
EnTXABT [21]: Enable Transmit Abort interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated to indicate 16 collisions occur while transmitting the
same packet.
EnNCS [20]: Enable No Carrier Sense interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated to indicate no carrier sense is presented during
transmission.
EnEXDEF [19]: Enable Defer interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated to indicate that the defer time exceeding
0.32768ms operated at 100Mbs/s or 3.2768ms operated at 10Mbs/s.
EnTXCP [18]: Enable Transmit Completion interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated when the MAC transmits, or discards one packet.
EnTXEMP [17]: Enable Transmit FIFO Empty interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated when MAC transmit FIFO becomes empty
(underflow) during a packet transmission.
EnTXINTR [16]: Enable Interrupt on Transmit interrupt
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