W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 158

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

This bit brings the watchdog timer into a known state. It helps reset the watchdog timer before a time-
out situation occurring. Failing to set WTR before time-out will initiates an interrupt if WTIE is set. If
WTRE is set, a watchdog timer reset will occur 512 clocks after time-out. This bit is self-clearing.
1 = Reset the contents of the watchdog timer
0 = Do not reset the contents of the watchdog timer
6.11 Advanced Interrupt Controller (AIC)
An interrupt temporarily changes the sequence of program execution to react to a particular event
such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC
Controller, and so on. The ARM7TDMI processor provides two modes of interrupt, the Fast Interrupt
(FIQ) mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception
is occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ
input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible
to ignore the FIQ and the IRQ by setting the F and I bits in the current program status register
(CPSR).
The W90N740 incorporates the advanced interrupt controller (AIC) that is capable of dealing with
the interrupt requests from a total of 32 different sources. Currently, only 18 interrupt sources are
defined. Each interrupt source is uniquely assigned to an interrupt channel. For example, the
watchdog timer interrupt is assigned to channel 1 and the general-purpose direct-access memory
access (GDMA) interrupt 0 to channel 17. The AIC implements a proprietary eight-level priority
scheme that differentiates the available 18 interrupt sources into eight priority levels. Interrupt sources
within the priority level 0 have the highest priority and the priority level 7 has the lowest. To work this
scheme properly, you must specify a certain priority level to each interrupt source during power-on
initialization; otherwise, the system shall behave unexpectedly. Within each priority level, interrupt
source that is positioned in a lower channel has a higher priority. Interrupt source that is active,
enabled, and positioned in the lowest channel within the priority level 0 is promoted to the FIQ.
Interrupt sources within the priority levels other than 0 can petition for the IRQ. The IRQ can be
preempted by the occurrence of the FIQ. Interrupt nesting is performed automatically by the AIC.
Though interrupt sources originated from the W90N740 itself are intrinsically high-level sensitive, the
AIC can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or
positive-edge triggered to each interrupt source.
The Features of the AIC (advanced interrupt controller):
18 interrupt sources, including 4 external interrupt sources
Programmable normal or fast interrupt mode (IRQ, FIQ)
Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
Programmable as either low-active or high-active for 4 external interrupt sources
Priority methodology is encoded to allow for interrupt daisy-chaining
Automatically mask out the lower priority interrupt during interrupt nesting
Automatically clear the interrupt flag when the interrupt source is programmed to be edge-
triggered
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W90N740CD/W90N740CDG
Publication Release Date: September. 19, 2005
Revision A7