W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 12

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

5. PIN DESCRIPTION
Table 5.1 W90N740 Pins Description
System Clock & Reset
TAP Interface
External Bus Interface
PIN NAME
EXTAL
XTAL
MCLK
nRESET
TCK
TMS
TDI
TDO
nTRST
A [24:22]
A [21:0]
D [31:16]
D [15:0]
nWBE [3:0]/
SDQM [3:0]
nSCS [1:0]
nSRAS
nSCAS
nSWE
MCKE
EMREQ
EMACK
nWAIT
nBTCS
nECS [3:0]
nOE
IO TYPE
IO
IO
IO
IO
IO
ID
IU
IU
IU
ID
IU
O
O
O
O
O
O
O
O
O
O
O
O
I
I
internal pull-down
internal pull-
down
internal pull-up
internal pull-up
internal pull-up
internal pull-up
PAD TYPE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Crystal Output
System Master Clock Out, SDRAM clock
System Reset, active-low
JTAG Test Clock,
JTAG Test Data out
Address Bus (MSB) of external memory and IO devices
Address Bus of external memory and IO devices
Data Bus (MSB) of external memory and IO device,
Data Bus (LSB) of external memory and IO device
Write Byte Enable for specific device(nECS[3:0]),
Data input/output Mask signal for SDRAM (nSCS[1:0]),
active-low These pins are always Output in normal mode,
and Input type in internal SRAM test mode.
SDRAM chip select for two external banks, active-low.
Row Address Strobe for SDRAM, active-low
Column Address Strobe for SDRAM, active-low
SDRAM Write Enable, active-low
SDRAM Clock Enable, active-high
External Master Bus Request
This is used to request external bus. When EMACK active,
indicates the bus grants the bus, chip drives all the output
pins of the external bus to high impedance.
External Bus Acknowledge
External Wait, active-low
ROM/Flash Chip Select, active-low
ROM/Flash, External Memory Output Enable, active-low
External Clock / Crystal Input
JTAG Test Mode Select,
JTAG Test Data in,
JTAG Reset, active-low,
External I/O Chip Select, active-low.
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W90N740CD/W90N740CDG
Publication Release Date: September. 19, 2005
DESCRIPTION
Revision A7