W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 150

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

PEI [2]: Parity Error Indicator
This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset
whenever the CPU reads the contents of the LSR.
OEI [1]: Overrun Error Indicator
An overrun error will occur only after the RX FIFO is full and the next character has been completely
received in the shift register. The character in the shift register is overwritten, but it is not transferred to
the RX FIFO. OE is indicated to the CPU as soon as it happens and is reset whenever the CPU reads
the contents of the LSR.
RFDR [0]: RX FIFO Data Ready
0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not
suggested).
Modem Status Register (MSR)
DCD#[7]:
RI#[6]:
DSR#[5]:
CTS#[4]:
DDCD [3]:
This bit is set whenever DCD# input has changed state, and it will be reset if the CPU reads the MSR.
TERI [2]: Tailing Edge of RI#
REGISTER
MSR
DCD#
7
0xFFF8.0018
ADDRESS
Complement version of Data Carrier Detect (nDCD#) input
Complement version of ring indicator (RI#) input
Complement version of data set ready (DSR#) input
Complement version of clear to send (CTS#) input
DCD# State Change
RI#
6
DSR#
5
R/W
R
MODEM Status Register
CTS#
4
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W90N740CD/W90N740CDG
DESCRIPTION
DDCD
3
Publication Release Date: September. 19, 2005
TERI
2
DDSR
1
RESET VALUE
0x0000.0000
Revision A7
DCTS
0