W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 78

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

CAM Enable Register (CAMEN_0, CAMEN_1)
The CAM enable register, CAMEN_x, indicates which CAM entries are valid, using a direct
comparison mode. Up to 16 entries, numbered 0 through 15, may be active, depending on the CAM
size. If the CAM is smaller than 16 entries, the higher bits are ignored.
CAMxEN (x: 15 ~ 0) [15:0] : CAM Enable bits
Default value: 0
Set the bits in this 16-bit value to selectively enable entry locations from 0 through 15. For example, bit
0 is associated with Entry CAM0, and bit 1 is associated with Entry CAM1, …etc. To disable an entry
location, clear the appropriate bit.
Note: The CAM13EN, CAM14EN, and CAM15EN has to be set for sending pause control packet.
CAM Address Registers (CAMxx_0, CAMxx_1)
There are 16 entries for the Destination Address (entries 0~12) and the Pause Control Packet (entries
13~15). For the destination address values, one destination address consists of 6 bytes with 2-word
access port.
To send a Pause Control Packet, write in the register set {CAM13M, CAM13L} with the destination
address, the {CAM14M, CAM14L} entry with the source address, and the {CAM15M, CAM15L} entry
with length/type, op-code, and operand, then set the SDPZ bit in the MCMDR (MAC Command
Register).
The CPU uses the CAM address register as a database for destination address. To activate the CAM
function, the appropriate enable bit has to be set in the CAMEN register.
CAMEN_0
CAMEN_1
REGISTER
CAM15EN CAM14EN CAM13EN CAM12EN CAM11EN CAM10EN
CAM7EN
31
23
15
7
0xFFF0.3004
0xFFF0.3804
CAM6EN
ADDRESS
30
22
14
6
CAM5EN
R/W
R/W
R/W
29
21
13
5
CAM4EN
CAM enable register
CAM enable register
28
20
12
4
Reserved
Reserved
- 75 -
W90N740CD/W90N740CDG
DESCRIPTION
CAM3EN
27
19
11
3
Publication Release Date: September. 19, 2005
CAM2EN
26
18
10
2
CAM9EN
CAM1EN
25
17
9
1
RESET VALUE
0x0000.0000
0x0000.0000
CAM8EN
CAM0EN
Revision A7
24
16
8
0