W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 35

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

The formula of output clock of PLL is:
F
F
F
NR：Input divider value (NR = INDV + 2)
NF：Feedback divider value (NF = FBDV + 2)
NO：Output divider value (NO = OTDV)
Clock Select Register (CLKSEL)
REGISTER
USBCKS RESERVED
OUT
OUT：
IN：
CLKSEL
USB
31
23
15
7
External clock into the Input Divider
= F
Output clock of Output Divider
INDV[4:0]
FBDV[8:0]
IN
∗
0xFFF0.000C
TIMER
NF
NR
ADDRESS
30
22
14
6
∗
Input Divider
NO
1
Feedback
FIN
Divider
EXTAL
(NR)
(NF)
PFD
GDMA
UART
29
21
13
5
R/W
R/W
Charge
Pump
Fig 6.2.6 System PLL block diagram
ECLKS
NATA
28
20
12
4
RESERVED
RESERVED
VCO
PLL
- 32 -
W90N740CD/W90N740CDG
OTDV[1:0]
Clock Select Register
Divider
Output
(NO)
EMC1
27
19
11
DESCRIPTION
3
480MHz
FOUT
EMC0
CLKS
26
18
10
2
CLKS[2:0]
Selector
48MHz
Divider
Clock
Gen
&
GP12
WDTS
USBCKS
25
17
ECLKS
9
1
1
0
0
1
RESET VALUE
0x0000.3FX8
Module
Internal
RESET
System
USB
Clock
WDT
24
16
8
0