W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 94

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

RxTHD [1:0]: Receive FIFO Upper threshold Register
Default value: 1h
Value setting:
This value controls the receive FIFO high threshold. If receiving packet number is greater than the
setting value, Rx DMA will request the arbiter to send data into memory.
MAC Interrupt Status Register (MISTA_0, MISTA_1)
The MAC event register is used as the Ethernet event register to generate interrupts and report events
recognized by MAC controller. When an event is recognized, the MAC controller sets the
corresponding MISTA bit. Interrupts are enabled by setting, and masked by clearing, the equivalent
bits in the MAC Interrupt Enable Register (MIEN). The MISTA bits are cleared by write ones; writing
zeros has no effect.
TxBErr [24]: Transmit Bus Error interrupt
Default value: 0
This field will be set if access error from EMC to memory (for example, address undefined in system) is
occurred. If the status and EnTxBErr in MIEN are both set, the EMC_TxINT will be triggered. If the
status is set, the Tx operation will be ceased and the software reset to reset the EMC is recommended.
MISTA_0
MISTA_1
REGISTER
Reserved
MMP
TDU
31
23
15
7
00b: Depend on the burst length setting
01b: 64 bytes (i.e. low threshold 32 bytes)
10b: 128 bytes (i.e. low threshold 64 bytes)
11b: 192 bytes (i.e. low threshold 96 bytes)
0xFFF0.30B4
0xFFF0.38B4
ADDRESS
CFR
LC
RP
30
22
14
6
NATErr
TXABT
ALIE
R/W
R/W
R/W
29
21
13
5
MAC Interrupt Status Register
MAC Interrupt Status Register
Reserved
NATOK
RXGD
NCS
28
20
12
4
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W90N740CD/W90N740CDG
DESCRIPTION
RxBErr
EXDEF
PTLE
27
19
11
3
Publication Release Date: September. 19, 2005
RXOV
TXCP
RDU
26
18
10
2
TXEMP
CRCE
DENI
25
17
9
1
RESET VALUE
0x0000.0000
0x0000.0000
Revision A7
RXINTR
TXINTR
TxBErr
DFOI
24
16
8
0