W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 44

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

REFEN [18]: Enable SDRAM refresh cycle for SDRAM bank0 & bank1
This bit set will start the auto-refresh cycle to SDRAM. The refresh rate is according to REFRAT bits.
REFMOD [17]: The refresh mode of SDRAM for SDRAM bank
Defines the refresh mode type of external SDRAM bank
0 = Auto refresh mode
1 = Self refresh mode
CLKEN [16]: Clock enable for SDRAM
Enables the SDRAM clock enable (CKE) control signal
0 = Disable (power down mode)
1 = Enable （Default）
REFRAT [15:3]: Refresh count value for SDRAM
The refresh period is calculated as
The SDRAM Controller automatically provides an auto refresh cycle for every refresh period
programmed into the REFRAT bits when the REFEN bit of each bank is set.
WAITVT [2:1]: Valid time of nWAIT signal
W90N740 recognizes the nEWAIT signal at the next “nth” MCLK rising edge after the nOE or nWBE
active cycle. WAITVT bits determine the n.
LITTLE [0] ：Read only, Little Endian mode
0 = EBI memory format is Big Endian mode
1 = EBI memory format is Little Endian mode
After power on reset, the content of LITTLE is the Power-On Setting value from D14 pin.
If pin D14 is pull-down, the external memory format is Big Endian mode.
If pin D14 is pull-up, the external memory format is Little Endian mode.
For more detail, refer to Power-On Setting of System Manager.
ROM/Flash Control Register （ROMCON）
REGISTER
ROMCON
0
0
1
1
0xFFF0.1004
WAITVT [2:1]
ADDRESS
period =
R/W
R/W
0
1
0
1
ROM/FLASH control register
fMCLK
value
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W90N740CD/W90N740CDG
DESCRIPTION
Publication Release Date: September. 19, 2005
NTH MCLK
1
2
3
4
RESET VALUE
0x0000.0XFC
Revision A7