W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 64

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

DCAEN [1] ： D-Cache enable
When set to “1”, Data cache operation is enabled.
D-Cache is disabled after reset.
ICAEN [0] ： I-Cache enable
When set to “1”, Instruction cache operation is enabled.
I-Cache is disabled after reset.
Cache Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
DRWB [7] ：Drain write buffer
Forces write buffer data to be written to main memory.
ULKS [6] ：Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in CAHADR register must be
specified.
ULKA [5] ：Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared to 0.
REGISTER
CAHCON
DRWB
Flush I-Cache and D-Cache
Load and lock I-Cache and D-Cache
Unlock I-Cache and D-Cache
Drain write buffer
31
23
15
7
0xFFF0.2004
ULKS
ADDRESS
30
22
14
6
ULKA
29
21
13
5
R/W Cache control register
R/W
LDLK
28
20
12
4
RESERVED
RESERVED
RESERVED
- 61 -
W90N740CD/W90N740CDG
FLHS
DESCRIPTION
27
19
11
3
Publication Release Date: September. 19, 2005
FLHA
26
18
10
2
DCAH
25
17
9
1
RESET VALUE
0x0000.0000
Revision A7
ICAH
24
16
8
0