W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 58

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

6.4
The W90N740 has an 8KB Instruction cache, 2KB Data cache, and 8 words write buffer. The I-Cache
and D-Cache are similar except the cache size. To enhance the hit ratio, these two caches are
configured two-way set associative addressing. Each cache has four words cache line size. When a miss
occurs, four words must be fetched consecutively from external memory. The replacement algorithm is a
LRU (Least Recently Used).
The W90N740 also provides a write buffer to improve system performance. The write buffer can buffer
up to eight words of data.
6.4.1
If I-Cache or D-Cache is disabled, it can be served as On-Chip RAM. If D-Cache is disabled, there has
2KB On-Chip RAM, its start address is 0xFFE02000. If I-Cache is disabled, there has 8KB On-Chip RAM
and the start address of this RAM is 0xFFE00000. If both the I-Cache and D-Cache are disabled, it has
10KB On-Chip RAM starting from 0xFFE00000.
The size of On-Chip RAM is depended on the I-Cache and D-Cache enable bits ICAEN, DCAEN in
Cache Control Register (CAHCON).
6.4.2
Although the cache affects the entire 2GB system memory, it is sometimes necessary to define non-
cacheable areas when the consistency of data stored in memory and the cache must be ensured. To
support this, the W90N740 provides a non-cacheable area control bit in the address field, A [31].
If A [31] in the ROM/FLASH, SDRAM, or external I/O bank’s access address is “0”, then the accessed
data is cacheable. If the A [31] value is “1”, the accessed data is non-cacheable.
6.4.3
The Instruction cache (I-cache) is an 8K bytes two-way set associative cache. The cache organization is
256 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory.
The cache access cycle begins with an instruction request from the instruction unit in the core. In the
case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the cache
initiates a burst read cycle on the internal bus with the address of the requested instruction. The first
word received from the bus is the requested instruction. The cache forwards this instruction to the
instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to
receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is
used to select a line when no empty lines are available.
ICAEN
Cache Controller
On-Chip RAM
0
0
1
1
Non-Cacheable Area
Instruction Cache
Table6.4.1 The size and start address of On-Chip RAM
DCAEN
0
1
0
1
10KB
Size
8KB
2KB
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W90N740CD/W90N740CDG
Publication Release Date: September. 19, 2005
ON-CHIP RAM
Unavailable
Start Address
0xFFE0.0000
0xFFE0.0000
0xFFE0.2000
Revision A7