W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 98

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

All the MGSTA bits are write ones clear.
TXHA [11]: Transmission Halted
Default value: 0
Set to indicate that the transmission is halt by clearing the TXON bit.
SQE [10]: Signal Quality Error
Default value: 0
Set to indicate a SQE.
PAU [9]: Pause Bit
Default value: 0
Set when transmission was delayed due to a remote Pause command.
DEF [8]: Deferred transmission
Default value: 0
This bit is set to indicate the network is busy.
CCNT [7:4]: Collision Count
Default value: 0
Four bits counter to indicate the number of collisions occurred before the frame is transmitted.
RXHA [1]: Reception Halted
Default value: 0
This bit is set if reception is halted by clearing RXON bit in the MAC Command Register (MCMDR).
CFR [0]: Control Frame Received
Default value: 0
This bit is set if (1) the packet received is a MAC control frame (type = 8808H), (2) if the CAM
recognizes the packet address, and (3) if the frame length is 64 bytes.
MAC Received Pause Count Register (MRPC_0, MRPC_1)
The received pause count register, MRPC, stores the value of the 16-bit received pause counter. It is
read only.
MRPC_0
MRPC_1
REGISTER
0xFFF0.30BC
0xFFF0.38BC
ADDRESS
R/W
R
R
MAC Receive Pause count register
MAC Receive Pause count register
DESCRIPTION
- 95 -
W90N740CD/W90N740CDG
Publication Release Date: September. 19, 2005
RESET VALUE
0x0000.0000
0x0000.0000
Revision A7