W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 95

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

W90N740CD/W90N740CDG
TDU [23]: Transmit Descriptor Unavailable interrupt
Default value: 0
This field will be set if the transmit descriptors owned to the TxDMA is unavailable. If the status and
EnTDU in MIEN are both set, the EMC_TxINT will be triggered. When it is set, the TxDMA operation will
be ceased till the user issues a write command to Transmit Start Demand register to restart the Tx
operation.
LC [22]: Late Collision
Default value: 0
This bit will be set if a collision occurs after 512 bit times.
TXABT [21]: Transmit Abort
Default value: 0
The bit is set to indicate 16 collisions occur while transmitting the same packet.
NCS [20]: No Carrier Sense
Default value: 0
Set to indicate no carrier sense is presented during transmission.
EXDEF [19]: Defer
Default value: 0
This bit is set to indicate that defer time exceeding 0.32768ms operated at 100Mbs/s and 3.2768ms
operated at 10Mbs/s. When the EnEXDEF in MIEN is set, the internal 15-bit counter will automatically
count the deferred bit time and generate interrupt when the counter overflows.
TXCP [18]: Transmit Completion
Default value: 0
This bit is set when the MAC transmits, or discards one packet.
TXEMP [17]: Transmit FIFO Empty
Default value: 0
Set when MAC transmitting FIFO becomes empty (underflow) during a packet transmission.
TXINTR [16]: Interrupt on Transmit
Default value: 0
This bit is set if transmission of a packet caused an interrupt condition.
CFR [14]: Control Frame Receive
Default value: 0
This field will be set if the incoming frame is a MAC control frame (type==8808h).
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