W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 83

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

W90N740CD/W90N740CDG
EnMMP [7]: Enable More Missed Packets interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated when the missed error counter rolls over.
EnRP [6]: Enable Runt Packet on Receive interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC receives a frame shorter less than 64
bytes.
EnALIE [5]: Enable Alignment Error interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the frame length in bits was not a multiple of
eight.
EnRXGD [4]: Enable Receive Good interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if a packet was successfully received with no
errors.
EnPTLE [3]: Enable Packet Too Long interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC received a frame longer than 1518
bytes (unless ALP in MCMDR is set).
EnRXOV [2]: Enable Receive FIFO Overflow interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the MAC receives FIFO was full when receiving a
frame.
EnCRCE [1]: Enable CRC Error interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the CRC at the end of a packet is not correct, or
else the PHY asserted Rx_er during packet reception.
EnRXINTR [0]: Enable Interrupt on Receive interrupt
Default value: 0
Set this bit to enable the interrupt, which is generated if the reception of a packet caused an interrupt to
be generated. This includes a good received interrupt, if the EnRXGD bit is set.
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