W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 20

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

6.2.4
6.2.4.1. Memory formats
The internal architecture is big endian. The little endian mode only support for external
memory. The W90N740 can be configured as big endian or little endian mode by pull up or down the
data D14 pin. If D14 is pull-up then it is a little endian mode, otherwise, it is a big endian mode.
Big Endian
In Big endian format, the W90N740 stores the most significant byte of a word at the lowest numbered
byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the
memory system connects to data lines 31 through 24.
For a word aligned address A, Fig6.2.2 shows how the word at address A, the half-word at addresses
A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the LITTLE
pin is Low.
Little Endian
In Little endian format, the lowest addressed byte in a word is considered the least significant byte of
the word and the highest addressed bye is the most significant. So the byte at address 0 of the
memory system connects to data lines 7 through 0.
For a word aligned address A, Fig6.2.3 shows how the word at address A, the half-word at addresses
A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when LITTLE pin
is High.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Byte at address A+3
Byte at address A
Data Bus Connection with External Memory
Half-word at address A+2
Half-word at address A
Fig. 6.2.3 Little endian addresses of bytes and half-words within words
Fig. 6.2.2 Big endian addresses of bytes and half-words within words
Byte at address A+1
Byte at address A+2
Word at address A
Word at address A
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W90N740CD/W90N740CDG
Byte at address A+2
Byte at address A+1
Publication Release Date: September. 19, 2005
Half-word at address A+2
Half-word at address A
8
8
7
7
Byte at address A+3
6
6
Byte at address A
5
5
4
4
3
3
Revision A7
2
2
1
1
0
0