W90N740CD WINBOND [Winbond], W90N740CD Datasheet - Page 130

• Manufacturer Part Number: W90N740CD
• Description: 32-Bit ARM7TDMI-Based Micro-Controller
• Manufacturer: WINBOND [Winbond]

Host Controller Interrupt Disable Register (HcInterruptDisable)
Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit
nchanged.
Register: HcInterruptStatus
HcInterrputDisable
BITS
29-7
30
31
REGISTER
0
1
2
3
4
5
6
RESET
0b
0b
0b
0b
0b
0b
0b
0h
0b
0b
0xFFF0.5014
ADDRESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W Host Controller Interrupt Disable Register
R/W
SchedulingOverrunEnable
0: Ignore
1: Disable interrupt generation due to Scheduling Overrun.
WritebackDoneHeadEnable
0: Ignore
1: Disable interrupt generation due to Write-back Done Head.
StartOfFrameEnable
0: Ignore
1: Disable interrupt generation due to Start of Frame.
ResumeDetectedEnable
0: Ignore
1: Disable interrupt generation due to Resume Detected.
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit will be ignored.
FrameNumberOverflowEnable
0: Ignore
1: Disable interrupt generation due to Frame Number Overflow.
RootHubStatusChangeEnable
0: Ignore
1: Disable interrupt generation due to Root Hub Status Change.
Reserved. Read/Write 0's
OwnershipChangeEnable
0: Ignore
1: Disable interrupt generation due to Ownership Change.
MasterInterruptEnable
Global interrupt disable. A write of ‘1’ disables all interrupts.
- 127 -
W90N740CD/W90N740CDG
DESCRIPTION
Publication Release Date: September. 19, 2005
DESCRIPTION
RESET VALUE
0x0000.0000
Revision A7