MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 115

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PLLS — PLL Select Bit (PLL output or crystal input frequency)
BCS[C:B:A] — Base Clock Select Bits
MCSA and MCSB — Module Clock Select Bits
The BCSx and MCSx bits can be changed with a single-write access. In combination, these bits can be
used to “throttle” the CPU clock rate without affecting the MCLK rate; timing and baud rates can remain
constant as the processor speed is changed to match system requirements. This can save overall system
power.
Freescale Semiconductor
PLLS selects the PLL after the LCKF flag is set.
These bits determine the frequency of SYSCLK. SYSCLK is the source clock for the MCU, including
the CPU and buses. See
output or the crystal input frequency as selected by the PLLS bit.
These bits determine the clock used by some sections of some of the modules such as the baud rate
generators of the SCIs, the timer counter, the RTI, and COP. See
clock and PCLK is an internal bus rate clock.
1 = PLL selected
0 = Crystal input selected
Table
BCSC:BCSB:BCSA
Table 11-3. Module Clock Selection
Table 11-2. Base Clock Selection
11-2. SYSCLK and is twice the bus rate. MUXCLK is either the PLL
MCS[B:A]
MC68HC812A4 Data Sheet, Rev. 7
000
001
010
011
100
101
110
111
00
01
10
11
MCLK
PCLK
--------------- -
PCLK
--------------- -
PCLK
--------------- -
PCLK
2
4
8
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
------------------------ -
MUXCLK
SYSCLK
128
16
32
64
2
4
8
Table
Registers and Reset Initialization
11-3. MCLK is the module
115