MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 29

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 2
Register Block
2.1 Overview
The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space
by manipulating bits REG15–REG11 in the INITRG register. INITRG establishes the upper five bits of the
register block’s 16-bit address.
The register block occupies the first 512 bytes of the 2-Kbyte block.
addressing.
2.2 Register Map
Freescale Semiconductor
$0000
$0001
$0002
$0003
$0004
$0005
$0006
Addr.
Register Name
Port A Data Direction
Port B Data Direction
Port C Data Direction
Port C Data Register
Port D Data Register
Port A Data Register
Port B Data Register
Register (DDRC)
Register (DDRA)
Register (DDRB)
See page 64.
See page 65.
See page 64.
See page 65.
See page 66.
See page 67.
See page 66.
(PORTC)
(PORTD)
(PORTA)
(PORTB)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 2-1. Register Map (Sheet 1 of 14)
DDRA7
DDRB7
DDRC7
Bit 7
PA7
PB7
PC7
PD7
0
0
0
0
0
0
0
MC68HC812A4 Data Sheet, Rev. 7
= Unimplemented
DDRA6
DDRB6
DDRC6
PC6
PD6
PA6
PB6
6
0
0
0
0
0
0
0
DDRC5
DDRA5
DDRB5
PA5
PB5
PC5
PD5
5
0
0
0
0
0
0
0
DDRC4
DDRA4
DDRB4
PA4
PB4
PC4
PD4
R
4
0
0
0
0
0
0
0
Figure 2-1
= Reserved
DDRA3
DDRB3
DDRC3
PA3
PB3
PC3
PD3
3
0
0
0
0
0
0
0
DDRA2
DDRB2
DDRC2
shows the default
PC2
PD2
PA2
PB2
2
0
0
0
0
0
0
0
U = Unaffected
DDRA1
DDRB1
DDRC1
PA1
PB1
PC1
PD1
1
0
0
0
0
0
0
0
DDRC0
DDRA0
DDRB0
Bit 0
PA0
PB0
PC0
PD0
0
0
0
0
0
0
0
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