MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 58

IC MCU 16BIT EEPROM 4K 112-LQFP

MC812A4CPVE8

Manufacturer Part Number
MC812A4CPVE8
Description
IC MCU 16BIT EEPROM 4K 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC812A4CPVE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
83
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC812A
Core
HC12
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
91
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Controller Family/series
68HC12
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Operating Modes and Resource Mapping
5.4 Mode and Resource Mapping Registers
This section describes the mode and resource mapping registers.
5.4.1 Mode Register
MODE controls the MCU operating mode and various configuration options. This register is not in the map
in peripheral mode.
Read:
Write:
SMODN, MODB, and MODA — Mode Select Special, B, and A Bits
ESTR — E-Clock Stretch Enable Bit
IVIS — Internal Visibility Bit
58
These bits show the current operating mode and reflect the status of the BKGD, MODB, and MODA
input pins at the rising edge of reset.
SMODN can be written only if SMODN = 0 (in special modes) but the first write is ignored. MODB and
MODA may be written once if SMODN = 1; anytime if SMODN = 0, except that special peripheral and
reserved modes cannot be selected.
ESTR determines if the E-clock behaves as a simple free-running clock or as a bus control signal that
is active only for external bus cycles.
Normal modes: Write once
Special modes: Write anytime
IVIS determines whether internal ADDR, DATA, R/W, and LSTRB signals can be seen on the external
bus during accesses to internal locations. If this bit is set in special narrow mode and EMD = 1 when
an internal access occurs, the data appears wide on port C and port D. This allows for emulation.
Visibility is not available when the part is operating in a single-chip mode.
1 = E stretches high during external access cycles and low during non-visible internal accesses.
0 = E never stretches (always free running).
1 = Internal bus operations are visible on external bus.
0 = Internal bus operations are not visible on external bus.
Special expanded narrow:
Normal expanded narrow:
Special expanded wide:
Anytime
Varies from bit to bit
Normal expanded wide:
Reset States
Special single-chip:
Normal single-chip:
Special peripheral:
Address: $000B
Read:
Write:
SMODN
Bit 7
0
0
0
0
1
1
1
Figure 5-1. Mode Register (MODE)
MODB
MC68HC812A4 Data Sheet, Rev. 7
6
0
0
1
1
0
0
1
MODA
5
0
1
0
1
0
1
1
ESTR
4
1
1
1
1
1
1
1
IVIS
3
1
1
1
1
0
0
0
2
0
0
0
0
0
0
0
0
EMD
Freescale Semiconductor
1
1
1
1
1
0
0
0
EME
Bit 0
1
1
1
1
0
0
0

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