MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 147

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.6 General-Purpose I/O Ports
Port S shares its pins with the multiple serial interface (MSI). In all modes, port S pins PS7–PS0 are
available for either general-purpose I/O or for SCI and SPI functions.
13.6.1 Port S Data Register
Read: Anytime
Write: Anytime
PS7–PS4 — Port S Data Bits 7–4
PS3–PS0 — Port S Data Bits 3–0
Freescale Semiconductor
Port S shares PS7–PS4 with SPI0.
Port S shares PS3–0 with SCI1 and SCI0.
SS is the SPI0 slave-select terminal.
SCK is the SPI0 serial clock terminal.
MOSI is the SPI0 master out, slave in terminal.
MISO is the SPI0 master in, slave out terminal.
TXD1 is the SCI1 transmit terminal.
RXD1 is the SCI1 receive terminal.
TXD0 is the SCI0 transmit terminal.
RXD0 is the SCI0 receive terminal.
Pin function:
Address:
Reading a port S bit when its data direction bit is clear returns the level of
the voltage on the pin. Reading a port S bit when its data direction bit is set
returns the level of the voltage of the pin driver input.
A write to a port S bit is stored in an internal latch. The latch drives the pin
only when the corresponding data direction bit is set.
Writes do not change the pin state when the pin is configured for SCI
output.
Reset:
Read:
Write:
$00D6
Bit 7
PS7
SS
Figure 13-3. Port S Data Register (PORTS)
SCK
PS6
6
MC68HC812A4 Data Sheet, Rev. 7
MOSI
PS5
5
NOTE
Unaffected by reset
MISO
PS4
4
TXD1
PS3
3
RXD1
PS2
2
TXD0
PS1
1
General-Purpose I/O Ports
RXD0
Bit 0
PS0
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