MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 41

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
$00CE
$00CF
$00D0
$00D1
$00D2
$00D3
$00D4
$00D5
$00D6
$00D7
$00D8
$00EF
$00F0
$00F1
Addr.
↓
SCI 1 Data Register High
SCI 1 Data Register Low
SPI 0 Control Register 1
SPI 0 Control Register 2
SPI Baud Rate Register
EEPROM Configuration
EEPROM Block Protect
Register Name
Port S Data Direction
Port S Data Register
Register (EEPROT)
SPI Status Register
Register (EEMCR)
SPI Data Register
Register (DDRS)
See page 174.
See page 174.
See page 186.
See page 187.
See page 188.
See page 189.
See page 190.
See page 147.
See page 148.
See page 74.
See page 75.
(SC1DRH)
(SC1DRL)
(SP0CR1)
(SP0CR2)
Reserved
Reserved
Reserved
(PORTS)
(SP0DR)
(SP0BR)
(SP0SR)
↓
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 2-1. Register Map (Sheet 13 of 14)
DDRS7
SPIE
SPIF
Bit 7
Bit 7
PS7
R8
R7
T7
R
R
R
0
0
0
0
0
0
0
1
1
1
1
MC68HC812A4 Data Sheet, Rev. 7
= Unimplemented
BPROT6
DDRS6
WCOL
SPE
Bit 6
PS6
T8
R6
T6
R
R
R
6
0
0
0
0
0
0
0
1
1
1
BPROT5
DDRS5
SWOM
Bit 5
PS5
R5
T5
R
R
R
5
0
0
0
0
0
0
0
0
0
1
1
1
BPROT4
DDRS4
MSTR
MODF
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Bit 4
PS4
R4
T4
R
R
R
R
4
0
0
0
0
0
0
0
0
1
1
1
= Reserved
BPROT3
DDRS3
CPOL
PUPS
Bit 3
PS3
R3
T3
R
R
R
3
0
0
1
0
0
0
0
0
1
1
1
EESWAI
BPROT2
DDRS2
CPHA
SPR2
RDS
Bit 2
PS2
R2
T2
R
R
R
2
0
1
0
0
0
0
0
1
1
U = Unaffected
PROTLCK
BPROT1
DDRS1
SSOE
SPR1
Bit 1
PS1
R1
T1
R
R
R
1
0
0
0
0
0
0
0
0
0
1
Register Map
BPROT0
DDRS0
EERC
LSBF
SPC0
SPR0
Bit 0
Bit 0
PS0
R0
T0
R
R
R
0
0
0
0
0
0
0
0
1
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