MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 48

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Central Processor Unit (CPU12)
3.6 Indexed Addressing Modes
The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index
register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode.
The postbyte and extensions do these tasks:
3.7 Opcodes and Operands
The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing
mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing
capabilities.
Only 256 opcodes would be available if the range of values were restricted to the number that can be
represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the
opcode map. Opcodes on the second page are preceded by an additional byte with the value $18.
To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension
bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop
primitives. Extension bytes contain additional program information such as addresses, offsets, and
immediate data.
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Specify which index register is used
Determine whether a value in an accumulator is used as an offset
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
Code (xb)
Postbyte
,r
n,r
–n,r
n,r
–n,r
[n,r]
n,–r
n,r–
A,r
B,r
D,r
[D,r]
Source Code
Syntax
Table 3-2. Summary of Indexed Operations
n,+r
n,r+
MC68HC812A4 Data Sheet, Rev. 7
5-bit constant offset n = –16 to +15
r can specify x, y, sp, or pc
Constant offset (9- or 16-bit signed)
z:0 = 9-bit with sign in LSB of postbyte(s)
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify x, y, sp, or pc
16-bit offset indexed-indirect
rr can specify x, y, sp, or pc
Auto pre-decrement/increment
or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify x, y, or sp (pc not a valid choice)
Accumulator offset (unsigned 8-bit or 16-bit)
aa:00 = A
rr can specify x, y, sp, or pc
Accumulator D offset indexed-indirect
rr can specify x, y, sp, or pc
1 = 16-bit
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr: 00 = X, 01 = Y, 10 = SP, 11 = PC
Comments
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