MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 159

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.5.4 Receiver
A block diagram of the SCI receiver is shown in
14.5.4.1 Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCCR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCDRH) is the ninth bit (bit 8).
Freescale Semiconductor
OR TRANSMITTER
FROM TXD PIN
RXD
LOOPS
RSRC
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out to the TXD pin. Setting TE after the stop
bit appears on TXD causes data previously written to the SCI data register
to be lost.
Toggle the TE bit for a queued idle character when the TDRE flag becomes
set and immediately before writing the next byte to the SCI data register.
CONTROL
LOOP
MODULE
SCI INTERRUPT REQUEST
SCI INTERRUPT REQUEST
CLOCK
SBR12–SBR0
Figure 14-5. SCI Receiver Block Diagram
BAUD DIVIDER
WAKE
RAF
RE
ILT
PE
PT
M
MC68HC812A4 Data Sheet, Rev. 7
RECOVERY
DATA
CHECKING
Figure
WAKEUP
NOTE
PARITY
LOGIC
INTERNAL BUS
IDLE
ILIE
RIE
14-5.
H
8
11-BIT RECEIVE SHIFT REGISTER
7
RDRF
SCI DATA REGISTER
OR
6
5
4
R8
FE
NF
PE
3
Functional Description
2
1
0
L
RWU
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