MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 66

IC MCU 16BIT EEPROM 4K 112-LQFP

MC812A4CPVE8

Manufacturer Part Number
MC812A4CPVE8
Description
IC MCU 16BIT EEPROM 4K 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet

Specifications of MC812A4CPVE8

Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
83
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
HC812A
Core
HC12
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
91
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Controller Family/series
68HC12
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Bus Control and Input/Output (I/O)
6.3.5 Port C Data Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
Bits PC7–PC0 correspond to data lines DATA15–DATA8. When this port is not used for external data
such as in single-chip mode, these pins can be used as general-purpose I/O. DDRC determines the
primary direction for each pin. In narrow expanded modes, DATA15–DATA8 and DATA7–DATA0 are
multiplexed into the MCU through port C pins on successive cycles. This register is not in the on-chip map
in expanded and peripheral modes.
When the MCU is operating in special expanded narrow mode and port C and port D are being used for
internal visibility, internal accesses produce full 16-bit information with DATA15–DATA8 on port C and
DATA7–DATA0 on port D. This allows the MCU to operate at full speed while making 16-bit access
information available to external development equipment in a single cycle. In this narrow mode, normal
16-bit accesses to external memory get split into two successive 8-bit accesses on port C alone.
6.3.6 Port C Data Direction Register
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
DDRC is not in the on-chip map in expanded and peripheral modes.
This register determines the primary direction for each port C pin when functioning as a general-purpose
I/O port.
66
Expanded wide and peripheral:
1 = Associated pin is an output.
0 = Associated pin is a high-impedance input.
Address: $0006
Expanded narrow: DATA15/7 DATA14/6 DATA13/5 DATA12/4 DATA11/3 DATA10/2
Reset:
Read:
Write:
Address: $0004
DDRC7
Reset:
Read:
Write:
Bit 7
0
Figure 6-6. Port C Data Direction Register (DDRC)
DATA15
Figure 6-5. Port C Data Register (PORTC)
Bit 7
PC7
DDRC6
0
6
0
MC68HC812A4 Data Sheet, Rev. 7
DATA14
PC6
DDRC5
6
0
5
0
DATA13
PC5
DDRC4
5
0
4
0
DATA12
PC4
DDRC3
4
0
3
0
DATA11
PC3
DDRC2
3
0
2
0
DATA10
PC2
DDRC1
2
0
1
0
DATA9/1
DATA9
Freescale Semiconductor
PC1
DDRC0
1
0
Bit 0
0
DATA8/0
DATA8
Bit 0
PC0
0

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