MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 52

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
interrupt timer ($FFF0). If an unimplemented vector address or a non-I-masked vector address (a value
higher than $F2) is written, then IRQ is the default highest priority interrupt.
4.5 Resets
There are five possible sources of reset:
Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset
without a system clock.
4.5.1 Power-On Reset
A positive transition on V
external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system voltage drops.
4.5.2 External Reset
The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin
rises to a logic 1 in less than nine E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then
released. Nine E-clock cycles later, it is sampled. If the pin is still held low, the CPU assumes that an
external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either
the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an external reset, hold the reset pin
low for at least 32 cycles. An external RC power-up delay circuit on the reset pin is not recommended
since circuit charge time can cause the MCU to misinterpret the type of reset that has occurred.
4.5.3 COP Reset
The MCU includes a computer operating properly (COP) system to help protect against software failures.
When COP is enabled, software must write $55 and $AA (in this order) to the COPRST register to keep
a watchdog timer from timing out. Other instructions may be executed between these writes. A write of
any value other than $55 or $AA or software failing to execute the sequence properly causes a COP reset
to occur.
4.5.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs.
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1. Power-on reset (POR)
2. External reset on the RESET pin
3. Reset from the alternate reset pin, ARST
4. The computer operating properly (COP) reset
5. Clock monitor reset
The first three reset sources all share the power-on reset vector and the last
two have their own vector for a total of three possible reset vectors.
DD
causes a power-on reset (POR). An external voltage level detector, or other
MC68HC812A4 Data Sheet, Rev. 7
NOTE
Freescale Semiconductor