MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 204

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ATD)
16.6.7 ATD Status Registers
Read: Anytime
Write: Special mode only
SCF — Sequence Complete Flag
CC2–CC0 — Conversion Counter Bits
CCF7–CCF0 — Conversion Complete Flags
204
In single conversion sequence mode (SCAN = 0 in ATDCTL5), SCF is set at the end of the conversion
sequence.
In continuous conversion mode (SCAN = 1 in ATDCTL5), SCF is set at the end of the first conversion
sequence.
Clear SCF by writing to control register 5 (ATDCTL5) to initiate a new conversion sequence. When the
fast flag clear enable bit, AFFC, is set, SCF is cleared after the first result register is read.
This 3-bit value reflects the value of the conversion counter pointer in either a 4-conversion or
8-conversion sequence. The pointer shows which channel is currently being converted and which
result register will be written next.
Each ATD channel has a CCF flag. A CCF flag is set at the end of the conversion on that channel.
Clear a CCF flag by reading status register 1 with the flag set and then reading the result register of
that channel. When the fast flag clear enable bit, AFFC, is set, reading the result register clears the
associated CCF flag even if the status register has not been read.
Address: $0066
Address: $0067
Reset:
Reset:
Read:
Read:
Write:
Write:
CCF7
Bit 7
SCF
Bit 7
0
0
Figure 16-10. ATD Status Register 2 (ATDSTAT2)
Figure 16-9. ATD Status Register 1 (ATDSTAT1)
= Unimplemented
= Unimplemented
CCF6
6
0
0
6
0
MC68HC812A4 Data Sheet, Rev. 7
CCF5
5
0
0
5
0
CCF4
4
0
0
4
0
CCF3
3
0
0
3
0
CCF2
CC2
2
0
2
0
CCF1
CC1
1
0
1
0
Freescale Semiconductor
CCF0
Bit 0
CC0
Bit 0
0
0