MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 211

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 17
Development Support
17.1 Introduction
This section describes:
17.2 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program information to the CPU when
instruction execution begins. The CPU12 always completely finishes executing an instruction before
beginning to execute the next instruction. Status signals IPIPE[1:0] provide information about data
movement in the queue and indicate when the CPU begins to execute instructions. This makes it possible
to monitor CPU activity on a cycle-by-cycle basis for debugging. Information available on the IPIPE[1:0]
pins is time multiplexed. External circuitry can latch data movement information on rising edges of the
E-clock signal; execution start information can be latched on falling edges.
of data on the pins.
Freescale Semiconductor
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Instruction queue
Queue tracking signals
Background debug mode (BDM)
Instruction tagging
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
IPIPE[1:0]
IPIPE[1:0]
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock
Mnemonic
Mnemonic
MC68HC812A4 Data Sheet, Rev. 7
Table 17-1. IPIPE Decoding
SOD
SEV
ALD
ALL
LAT
INT
—
—
No movement
Latch data from bus
Advance queue and load from bus
Advance queue and load from latch
No start
Start interrupt sequence
Start even instruction
Start odd instruction
Meaning
Meaning
Table 17-1
(1)
(2)
shows the meaning
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