MC812A4CPVE8 Freescale Semiconductor, MC812A4CPVE8 Datasheet - Page 123

• Manufacturer Part Number: MC812A4CPVE8
• Description: IC MCU 16BIT EEPROM 4K 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC812A4CPVE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 83
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: EEPROM
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: HC812A
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Controller Family/series: 68HC12
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Setting a force output compare bit, FOCx, causes an immediate output compare on channel x. A forced
output compare does not set the channel flag.
An output compare on channel 7 overrides output compares on all other output compare channels. A
channel 7 output compare causes any unmasked bits in the output compare 7 data register to transfer to
the timer port data register. The output compare 7 mask register masks the bits in the output compare 7
data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the
timer counter. A channel 7 output compare can reset the timer counter even if the OC7/PAI pin is being
used as the pulse accumulator input.
An output compare overrides the data direction bit of the output compare pin but does not change the
state of the data direction bit.
Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
12.4.4 Pulse Accumulator
The pulse accumulator (PA) is a 16-bit counter that can operate in two modes:
The PA mode bit, PAMOD, selects the mode of operation.
The minimum pulse width for the PAI input is greater than two module clocks.
12.4.4.1 Event Counter Mode
Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin
increments the PA. The PA edge bit, PEDGE, selects falling edges or rising edges to increment the PA.
An active edge on the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables
the PAIF flag to generate interrupt requests.
The PA counter registers, TIMPACNTH/L, reflect the number of active input edges on the PAI pin since
the last reset.
The PA overflow flag, PAOVF, is set when the PA rolls over from $FFFF to $0000. The PA overflow
interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
Freescale Semiconductor
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Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI
Gated time accumulation mode — Counting pulses from a divide-by-64 clock
The PAI input and timer channel 7 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 7 output mode
and output level bits, OM7 and OL7. Also clear the channel 7 output
compare 7 mask bit, OC7M7.
The PA can operate in event counter mode even when the timer enable bit,
TE, is clear.
MC68HC812A4 Data Sheet, Rev. 7
NOTE
NOTE
Functional Description
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