PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 114

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F47J53 FAMILY
7.4
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased;
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
DS39964B-page 114
Required
Sequence
Erasing Flash Program Memory
ERASE_ROW
ERASING FLASH PROGRAM MEMORY
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
Preliminary
; load TBLPTR with the base
; address of the memory block
; enable write to memory
; enable Erase operation
; disable interrupts
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
7.4.1
The sequence of events for erasing a block of internal
program memory location is:
1.
2.
3.
4.
5.
6.
7.
8.
Load Table Pointer register with address of row
being erased.
Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the erase cycle.
The CPU will stall for the duration of the erase
for T
Re-enable interrupts.
IE
(see parameter D133B).
FLASH PROGRAM MEMORY
ERASE SEQUENCE
 2010 Microchip Technology Inc.