PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 182

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F47J53 FAMILY
REGISTER 11-3:
DS39964B-page 182
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-5
bit 4-3
bit 2
bit 1-0
Note 1:
BUSY
R-0
This register is only available on 44-pin devices.
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
10 = No interrupt generated, processor stall activated
01 = Interrupt generated at the end of the read/write cycle
00 = No interrupt generated
INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR<15,13:0> by 1 every read/write cycle
01 = Increment ADDR<15,13:0> by 1 every read/write cycle
00 = No increment or decrement of address
MODE16: 8/16-Bit Mode bit
1 = 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers
0 = 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer
MODE<1:0>: Parallel Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCSx, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx and PMD<7:0>)
IRQM1
R/W-0
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)
W = Writable bit
‘1’ = Bit is set
IRQM0
R/W-0
INCM1
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INCM0
R/W-0
MODE16
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
MODE1
R/W-0
MODE0
R/W-0
bit 0
(1)