PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 191
![IC PIC MCU 128KB FLASH 28QFN](/photos/19/6/190629/4733462_sml.jpg)
PIC18LF27J53-I/ML
Manufacturer Part Number
PIC18LF27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/ML
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF27J53-I/ML
Manufacturer:
ATMEL
Quantity:
101
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 191 of 586
- Download datasheet (6Mb)
11.2.5
In the Addressable Parallel Slave Port mode
(
two extra inputs, PMA<1:0>, which are the address
lines 1 and 0. This makes the 4-byte buffer space
directly addressable as fixed pairs of read and write
buffers. As with Legacy Buffered mode, data is output
from PMDOUT1L, PMDOUT1H, PMDOUT2L and
PMDOUT2H, and is read in PMDIN1L, PMDIN1H,
PMDIN2L and PMDIN2H. Table 11-1 provides the
buffer addressing for the incoming address to the input
and output registers.
FIGURE 11-6:
11.2.5.1
When chip select is active and a read strobe occurs
(PMCSx = 1 and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 11-1 provides the corresponding
FIGURE 11-7:
2010 Microchip Technology Inc.
PMMODEH<1:0> = 01), the module is configured with
PMD<7:0>
PMA<1:0>
PMCSx
PMWR
Master
PMPIF
PMD<7:0>
PMA<1:0>
PMRD
OBE
ADDRESSABLE PARALLEL SLAVE
PORT MODE
PMCS1
PMWR
PMRD
READ FROM SLAVE PORT
Address Bus
Data Bus
Control Lines
PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE
PARALLEL SLAVE PORT READ WAVEFORMS
Preliminary
PMD<7:0>
PMA<1:0>
PMCS1
PMRD
PMWR
PIC18F47J53 FAMILY
TABLE 11-1:
output registers and their associated address. When an
output buffer is read, the corresponding OBxE bit is set.
The OBxE flag bit is set when all the buffers are empty.
If any buffer is already empty, OBxE = 1, the next read
to that buffer will generate an OBUF event.
Address
Decode
Write
PMA<1:0>
00
01
10
11
PIC18F Slave
PMDOUT1L (0)
PMDOUT1H (1)
PMDOUT2H (3)
PMDOUT2L (2)
|
Q4
SLAVE MODE BUFFER
ADDRESSING
PMDOUT2H((3)
PMDOUT1H (1)
PMDOUT1L (0)
PMDOUT2L (2)
|
Register
Q1
(Buffer)
Output
Address
Decode
Read
|
Q2
PMDIN1H (1)
PMDIN2H (3)
PMDIN1L (0)
PMDIN2L (2)
|
DS39964B-page 191
Q3
Input Register
PMDIN1H (1)
PMDIN2H (3)
PMDIN1L (0)
PMDIN2L (2)
(Buffer)
|
Q4
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