PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 51

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

4.3
The power-managed Sleep mode is identical to the
legacy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep mode. If
the WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
FIGURE 4-5:
FIGURE 4-6:
 2010 Microchip Technology Inc.
Peripheral
Program
Counter
OSC1
Sleep
Clock
Clock
CPU
Note 1: T
CPU Clock
PLL Clock
Peripheral
Program
Sleep Mode
Counter
Output
OSC1
Clock
Q1
Q2
OST
PC
Q3
= 1024 T
Wake Event
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1
Q1
OSC
T
OST
; T
PLL
(1)
= 2 ms (approx). These intervals are not shown to scale.
PC
T
PLL
OSTS Bit Set
(1)
Preliminary
Q2 Q3 Q4 Q1 Q2
PC + 2
PIC18F47J53 FAMILY
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the FSCM is enabled (see Section 28.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.
PC + 2
Q3 Q4 Q1 Q2
PC + 4
Q3 Q4
Q1 Q2 Q3 Q4
PC + 6
DS39964B-page 51