PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 330

IC PIC MCU 128KB FLASH 28QFN

PIC18LF27J53-I/ML

Manufacturer Part Number
PIC18LF27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF27J53-I/ML
Manufacturer:
ATMEL
Quantity:
101
PIC18F47J53 FAMILY
FIGURE 20-18:
DS39964B-page 330
Note:
SDAx
SCLx
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPxBUF did not occur.
2
C Master mode, does not allow queueing
MSSPx BLOCK DIAGRAM (I
SDAx In
Bus Collision
SCLx In
Read
MSb
Write Collision Detect
End of XMIT/RCV
Start bit, Stop bit,
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPxBUF
SSPxSR
Generate
Preliminary
2
C™ MASTER MODE)
LSb
Write
The following events will cause the MSSP Interrupt
Flag bit, SSPxIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmitted
• Repeated Start
Clock
Data Bus
Shift
Internal
Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1)
Set SSPxIF, BCLxIF
Reset ACKSTAT, PEN (SSPxCON2)
 2010 Microchip Technology Inc.
SSPxADD<6:0>
SSPM<3:0>
Generator
Baud
Rate

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