PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 582
![IC PIC MCU 128KB FLASH 28QFN](/photos/19/6/190629/4733462_sml.jpg)
PIC18LF27J53-I/ML
Manufacturer Part Number
PIC18LF27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/ML
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF27J53-I/ML
Manufacturer:
ATMEL
Quantity:
101
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 582 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
TSTFSZ............................................................................. 499
Two-Speed Start-up .................................................. 441, 455
Two-Word Instructions
TXSTAx Register
U
Ultra Low-Power Wake-up .................................................. 61
Universal Serial Bus.......................................................... 379
USB Specifications............................................................ 531
USB. See Universal Serial Bus.
DS39964B-page 582
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Timer0 and Timer1 External Clock
Requirements............................................................ 539
USB Full-Speed Requirements ................................. 553
USB Low-Speed Requirements ................................ 553
Example Cases ........................................................... 87
BRGH Bit .................................................................. 349
Address Register (UADDR) ...................................... 387
Associated Registers ................................................ 403
Buffer Descriptor Table ............................................. 388
Buffer Descriptors ..................................................... 388
Endpoint Control ....................................................... 386
External Pull-up Resistors......................................... 384
Eye Pattern Test Enable ........................................... 384
Firmware and Drivers................................................ 403
Frame Number Registers.......................................... 387
Internal Pull-up Resistors .......................................... 384
Internal Transceiver .................................................. 382
Interrupts ................................................................... 394
Oscillator Requirements............................................ 403
Overview ........................................................... 379, 404
Ping-Pong Buffer Configuration ................................ 384
Power Modes ............................................................ 400
RAM .......................................................................... 387
Status and Control .................................................... 380
UFRMH:UFRML Registers ....................................... 387
Requirements............................................ 537, 538
Address Validation ............................................ 391
Assignment in Different Buffering Modes.......... 393
BDnSTAT Register (CPU Mode) ...................... 389
BDnSTAT Register (SIE Mode) ........................ 391
Byte Count ........................................................ 391
Memory Map ..................................................... 392
Ownership......................................................... 388
Ping-Pong Buffering.......................................... 392
Register Summary ............................................ 393
Status and Configuration .................................. 388
and USB Transactions ...................................... 394
Class Specifications and Drivers ...................... 405
Descriptors........................................................ 405
Enumeration...................................................... 405
Frames.............................................................. 404
Layered Framework .......................................... 404
Power................................................................ 404
Speed................................................................ 405
Transfer Types.................................................. 404
Bus Power Only ................................................ 400
Dual Power with Self-Power Dominance .......... 400
Self-Power Only ................................................ 400
Transceiver Current Consumption .................... 401
Memory Map ..................................................... 387
Preliminary
V
Voltage Reference Specifications..................................... 529
Voltage Regulator (On-Chip) ............................................ 453
W
Watchdog Timer (WDT)............................................ 441, 451
WCOL ....................................................... 333, 334, 335, 338
WCOL Status Flag.................................... 333, 334, 335, 338
WWW Address ................................................................. 583
WWW, On-Line Support ....................................................... 9
X
XORLW............................................................................. 499
XORWF ............................................................................ 500
Operation in Sleep Mode .......................................... 454
Associated Registers ................................................ 452
Control Register........................................................ 451
During Oscillator Failure ........................................... 456
Programming Considerations ................................... 451
2010 Microchip Technology Inc.
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