PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 377

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 22-3:
FIGURE 22-4:
22.7
The A/D Converter in the PIC18F47J53 family of
devices includes a self-calibration feature, which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform an off-
set calibration and store the result internally. Thus,
subsequent offsets will be compensated.
Example 22-1 provides an example of a calibration
routine.
 2010 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
1
A/D Converter Calibration
T
T
CY
Set GO/DONE bit
Automatic
Acquisition
Time
ACQT
Holding capacitor is disconnected from analog input (typically 100 ns)
2
- T
AD
Cycles
Conversion starts
T
3
AD
A/D CONVERSION T
A/D CONVERSION T
1 T
4
AD
b9
2 T
(Holding capacitor is disconnected)
Conversion starts
1
AD
b8
3 T
b9
2
AD
Next Q4: ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
b7
Next Q4: ADRESH/ADRESL are loaded, GO/DONE bit is cleared,
4 T
b8
3
AD
AD
AD
b6
5 T
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
ADIF bit is set, holding capacitor is reconnected to analog input.
ADIF bit is set, holding capacitor is connected to analog input.
b7
4
AD
b5
6 T
T
5
b6
AD
AD
b4
PIC18F47J53 FAMILY
7 T
Cycles
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
b5
6
AD
b3
8
b4
T
7
AD
b2
9 T
b3
8
AD
b1
10
ACQ
ACQ
T
b2
9
AD
b0
11
= 0)
= 4 T
10
b1
AD
DS39964B-page 377
b0
)
11