PIC18LF27J53-I/ML Microchip Technology, PIC18LF27J53-I/ML Datasheet - Page 150

• Manufacturer Part Number: PIC18LF27J53-I/ML
• Description: IC PIC MCU 128KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF27J53-I/ML

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.75 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Digital Ic Case Style: QFN
• Supply Voltage Range: 1.8V To 3.6V
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F47J53 FAMILY
TABLE 10-5:
DS39964B-page 150
RB4/CCP4/
PMA1/KBI0/
SCK1/SCL1/
RP7
RB5/CCP5/
PMA0/KBI1/
SDI1/SDA1/
RP8
RB6/CCP6/
KBI2/PGC/RP9
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
Pin
2:
3:
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting
the appropriate bits in the ANCON1 register.
All other pin functions are disabled when ICSP™ or ICD is enabled.
Available only on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and PIC18LF47J53).
PORTB I/O SUMMARY (CONTINUED)
Function
CCP4
CCP5
PMA0
CCP6
PMA1
SCK1
SDA1
SCL1
SDI1
KBI0
KBI1
KBI2
PGC
RB4
RP7
RB5
RP8
RB6
RP9
(3)
(3)
(3)
(3)
Setting
TRIS
0
1
1
0
x
1
1
0
1
0
1
0
0
1
1
0
x
1
1
1
0
1
0
0
1
1
0
1
x
1
0
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL/
ST/TTL/
SMBus
SMBus
Type
DIG
TTL
DIG
DIG
TTL
DIG
I
DIG
DIG
DIG
TTL
DIG
DIG
TTL
I
DIG
DIG
DIG
TTL
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
2
2
C/
C/
Preliminary
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when the RBPU bit is
cleared. Disabled when analog input is enabled.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Interrupt-on-change pin.
Parallel Master Port io_addr_in<1>.
Parallel Master Port address.
I
I
Remappable Peripheral Pin 7 input.
Remappable Peripheral Pin 7 output.
LATB<5> data output.
PORTB<5> data input; weak pull-up when the RBPU bit is
cleared.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Interrupt-on-change pin.
SPI data input (MSSP1 module).
I
I
Remappable Peripheral Pin 8 input.
Remappable Peripheral Pin 8 output.
LATB<6> data output.
PORTB<6> data input; weak pull-up when the RBPU bit is
cleared.
Capture input.
Compare/PWM output.
Interrupt-on-change pin.
Serial execution (ICSP™) clock input for ICSP and ICD
operation.
Remappable Peripheral Pin 9 input.
Remappable Peripheral Pin 9 output.
2
2
2
2
C™ clock input (MSSP1 module).
C clock output (MSSP1 module).
C data input (MSSP1 module).
C/SMBus.
(2)
Description
 2010 Microchip Technology Inc.
(1)